Voltage multiplier circuit

ABSTRACT

A voltage multiplier circuit includes a voltage-to-current converter, a current multiplier, and load devices. The voltage-to-current converter receives a differential input voltage, and produces a differential current. The differential current is received by the current multiplier, which produces a scaled output current. The amount of scaling is provided by a digital control word. Load devices produce a differential output voltage from the scaled output current. Multiple voltage-to-current converters and current multipliers can be coupled in parallel so that the scaled output currents sum.

FIELD

[0001] The present invention relates generally to amplifiers, and morespecifically to amplifiers with programmable gain.

BACKGROUND

[0002] Amplifiers are commonly used to produce an output voltage or anoutput current in response to an input voltage or an input current.Voltage amplifiers receive an input voltage and produce an outputvoltage. Current amplifiers receive an input current and produce anoutput current. Other types of amplifiers also exist. For example, atransconductance amplifier receives an input voltage and produces anoutput current.

[0003]FIG. 1 shows a prior art amplifier circuit. Amplifier circuit 100includes operational amplifier (op-amp) 102, feedback resistor (R_(f))104, and input resistors (R₁, R₂) 106 and 108. Amplifier circuit 100produces an output voltage (V_(OUT)) on node 110 from input voltages(V_(IN1), V_(IN2)) on nodes 112 and 114. The output voltage satisfiesthe following equation: $\begin{matrix}{V_{OUT} = {{\left( \frac{- R_{f}}{R_{1}} \right)V_{IN1}} + {\left( \frac{- R_{f}}{R_{2}} \right)V_{IN2}}}} & (1)\end{matrix}$

[0004] As shown in equation (1) above, amplifier circuit 100 scales (or“multiplies”) each input voltage by a constant value and sums the scaledvoltage values. The constant values used to scale the input voltages areequal to a ratio of resistance values. By varying the resistance valuesof resistors 104, 106, and 108, the input voltage scaling can bechanged.

[0005] As is known in the art, amplifier circuit 100 has many uses. Itis also known in the art that amplifier circuit cannot operate atextremely high frequencies, in part because op-amp 102 usually includescompensation circuits to avoid instability, and these compensationcircuits tend to limit the frequency at which the op-amp can operate.

[0006] Other example circuits that provide voltage multiplicationinclude the “Gilbert cell” as described in chapter eight of: David AJohns & Ken Martin, “Analog Integrated Circuit Design,” (1997).

[0007] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art formethods and apparatus to provide amplifiers and multipliers that operateat high frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 shows a prior art voltage amplifier;

[0009]FIG. 2 shows an integrated circuit with a voltage multiplier;

[0010]FIG. 3 shows a voltage multiplier;

[0011]FIG. 4 shows a programmable current mirror; and

[0012]FIG. 5 shows an integrated circuit having a voltage multiplierwith multiple inputs.

DESCRIPTION OF EMBODIMENTS

[0013] In the following detailed description of the embodiments,reference is made to the accompanying drawings which show, by way ofillustration, specific embodiments in which the invention may bepracticed. In the drawings, like numerals describe substantially similarcomponents throughout the several views. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe present invention. Moreover, it is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described in one embodiment may be included within otherembodiments. The following detailed description is, therefore, not to betaken in a limiting sense, and the scope of the present invention isdefined only by the appended claims, along with the full scope ofequivalents to which such claims are entitled.

[0014]FIG. 2 shows an integrated circuit with a voltage multiplier.Integrated circuit 200 includes voltage-to-current (V-I) converter 202,current multiplier 208, and load devices 214 and 216. The combination ofV-I converter 202, current multiplier 208, and load devices 214 and 216forms a voltage multiplier where V_(OUT) is a multiple of V_(IN), V_(IN)is a differential input voltage impressed on nodes 220 and 222. V-Iconverter 202 converts the differential input voltage to a differentialcurrent on nodes 204 and 206. Current multiplier 208 receives thedifferential input current on nodes 204 and 206, and produces adifferential output current on nodes 210 and 212. Load devices 214 and216 receive the currents on nodes 210 and 212, and produce thedifferential output voltage V_(OUT).

[0015] In some embodiments, V-I converter 202 produces a differentialoutput current (I₁) on nodes 204 and 206 that varies linearly withchanges in the input voltage V_(IN). For example, as shown in FIG. 2,the current on nodes 204 and 206 satisfies the equation:

I₁=αV_(IN)  (2)

[0016] where αis a constant. In some embodiments, I₁ is substantiallylinear over a wide range of differential input voltage values. Exampleembodiments of a V-I converter are described with reference to FIG. 3below.

[0017] Current multiplier 208 includes an input side, an output side,and a digital input port. The input side of current multiplier 208 iscoupled to V-I converter 202 through nodes 204 and 206; the output sideis coupled to load devices 214 and 216 through nodes 210 and 212; anddigital input port 223 is coupled to node 224.

[0018] Current multiplier 208 produces a differential output current onnodes 210 and 212. The differential output current on nodes 210 and 212is equal to the differential current on nodes 204 and 206 scaled by ascale factor (K_(B)). For example, the differential output current onnodes 210 and 212 satisfies the equation:

I_(B)=K_(B)I₁=K_(b)αV_(IN)  (3)

[0019] The scale factor is controlled by a digital word (B) on node 224.Node 224 is shown as “n” bits wide to signify that any number of bitscan be included in the digital word B. As the value of B is increased,K_(B) is increased, and the differential output current on nodes 210 and212 is also increased. Likewise, when the value of B is decreased, K_(B)is decreased, and the differential output current on nodes 210 and 212is also decreased. Example embodiments of a current multiplier arediscussed below with reference to FIGS. 3 and 4.

[0020] Load devices 214 and 216 develop voltages on nodes 210 and 212 asa result of differential current I_(B). In some embodiments, loaddevices 214 and 216 produce a differential output voltage V_(OUT) thatvaries linearly with variations in differential current I_(B). In theseembodiments, the output voltage satisfies the equation:

V_(OUT)=R_(LOAD)I_(B)=R_(LOAD)K_(B)αV_(IN)  (4)

[0021] where R_(LOAD) is equal to the equivalent resistance of loaddevices 214 and 216. In some embodiments, load devices 214 and 216 areresistors with a resistance value of R_(LOAD). In other embodiments,load devices 214 and 216 are active devices such as transistors with anequivalent resistance value of R_(LOAD).

[0022] The voltage multiplier shown in FIG. 2 is a fully differentialsystem. For example, the input and output voltages are differential, asare the currents on internal nodes. By being fully differential, commonmode effects can be substantially ignored. For example, in embodimentsrepresented by FIG. 2, the output voltage has a common mode component,but the effects of the common mode component are substantially ignoredbecause the output voltage is measured as a difference between twonodes.

[0023] In some embodiments, the voltage multiplier is a single-endedsystem. In these embodiments, V-I converter 202 receives an inputvoltage on a single node and produces a current on one node. Currentmultiplier 208 receives one current and produces a multiplied outputcurrent on a single node, and one load device produces a single endedoutput voltage. Single-ended embodiments are useful in systems that cantolerate common mode variations in the output voltage.

[0024] In other embodiments, the voltage multiplier is a combination ofdifferential and single-ended systems. For example, in some embodiments,a differential input voltage is received, but a single-ended current isproduced by the V-I converter and a single load device is utilized toproduce a single-ended output voltage. In other embodiments, asingle-ended input voltage is received, and differential currents areproduced to provide a differential output voltage.

[0025]FIG. 3 shows a voltage multiplier. Voltage multiplier 300 includestransistors 302, 304, and 310, programmable current mirrors 320 and 322,and load resistors 324 and 326. Voltage multiplier 300 representsembodiments of the voltage multiplier circuit within integrated circuit200 (FIG. 2). Transistors 302, 304, and 310 form a V-I convertercorresponding to V-I converter 202 (FIG. 2); programmable currentmirrors 320 and 322 correspond to current multiplier 208 (FIG. 2); andload resistors 324 and 326 correspond to load devices 214 and 216 (FIG.2).

[0026] Transistors 302 and 304 form a differential pair of transistorsthat convert the input voltage V_(IN) to a differential current on nodes204 and 210. Transistor 310 is a tail current device that receives abias voltage (VBIAS) and sources a substantially constant current to thedifferential pair of transistors. As V_(IN) is varied, thesource-to-gate voltage on transistors 302 and 304 is varied, and thetail current from transistor 310 is varied between nodes 204 and 210.

[0027] In embodiments represented by FIG. 3, transistors 302, 304, and310 are p-channel metal oxide semiconductor field effect transistors(PMOSFETs). In other embodiments, other types of transistors are used.For example, in some embodiments, junction field effect transistors(JFET) are used, and in other embodiments, bipolar junction transistors(BJT) are used. As used herein, the term “p-channel transistor” refersto any transistor having an p-doped channel. Transistors 302, 304, and310 are examples of p-channel transistors.

[0028] Resistors 306 and 308 are source degeneration resistors. Ascurrent passes through resistors 306 and 308, a voltage drops acrossthem, leaving a smaller voltage to drop between the source and gate oftransistors 302 and 304. This can increase the useful input voltageswing. In some embodiments, resistors 306 and 308 are omitted. In theseembodiments, an effect similar to that provided by resistors 306 and 308can be provided by the source resistance of transistors 302 and 304.

[0029] In the embodiments represented by FIG. 3, the V-I converterutilizes p-channel transistors for both the tail current device and thedifferential pair of transistors. In other embodiments, n-channeltransistors are used. For example, an n-channel tail current device canbe coupled to a lower voltage supply node, and an n-channel differentialpair of transistors can be coupled to the n-channel tail current device.As used herein, all descriptions of circuits that include p-channeltransistors also describe equivalent circuits that utilize n-channeltransistors.

[0030] As described above, transistors 302, 304, and 310 form a V-Iconverter that corresponds to V-I converter 202 (FIG. 2). The V-Iconverter shown in FIG. 3 represents but a few of the many V-I converterembodiments. In some embodiments, different V-I converter circuits areused. Any V-I converter embodiment can be utilized without departingfrom the scope of the present invention.

[0031] Programmable current mirrors 320 and 322 form a differentialcurrent multiplier corresponding to current multiplier 208 (FIG. 2).Programmable current mirror 320 receives an input current on node 204from transistor 302, and produces an output current on node 210.Programmable current mirror 322 receives an input current on node 206from transistor 304, and produces an output current on node 212.Programmable current mirrors 320 and 322 include digital input ports 321and 323, respectively. Both digital input ports receive the digitalcontrol word B on node 224. As described above with reference to FIG. 2,the digital control word B controls the amount of current gain providedby programmable current mirrors 320 and 322. Example embodiments ofprogrammable current mirrors are described with reference to FIG. 4below.

[0032] Load resistors 324 and 326 are examples of load devices 214 and216 (FIG. 2). In some embodiments, load resistors 324 and 326 arereplaced with active devices, such as diode-connected transistors toprovide a very high impedance load. In other embodiments, load resistors324 and 326 are omitted, and voltage multiplier 300 becomes atransconductance multiplier that receives a voltage and produces acurrent. In these embodiments, the output of the circuit is thedifferential current provided on nodes 210 and 212.

[0033]FIG. 4 shows a programmable current mirror. Programmable currentmirror 320 includes diode-connected control transistor 416 and currentsource transistors 408, 424, 434, and 444. The term “diode-connected” asused herein, refers to a transistor that has a gate tied to a drain,such that the gate-to-source voltage and the drain-to-source voltage areequal. Diode-connected transistor 416 receives the input current(I_(IN)) on node 204, and provides a bias voltage to the current sourcetransistors on node 417. Each of current source transistors 408, 424,434, and 444 are part of a selectable current source circuit. Forexample, current source transistor 408 is part of selectable currentsource circuit 414. Selectable current source circuit 414 also includesselect transistors 402 and 406, and inverter 410. As shown in FIG. 4,select transistor 402 is coupled source-to-drain between the gate ofcontrol transistor 416 and the gate of current source transistor 408.Select transistor 408 is coupled source-to-drain between the gate ofcurrent source transistor 408 and a reference node.

[0034] Selectable current source circuit 414 is “selected” when signalB0 is asserted on node 412. When signal B0 is asserted, selecttransistor 402 turns on and select transistor 406 turns off, therebyproviding the bias voltage on node 417 to current source transistor 408.When the bias voltage is provided to current source transistor 408,current source transistor 408 contributes to the output current(I_(OUT)) on node 210. Selectable current source circuit 414 is“de-selected” when signal B0 is de-asserted on node 412. When B0 isde-asserted, select transistor 402 turns off and select transistor 406turns on, thereby providing a reference potential to current sourcetransistor,408 and turning it off.

[0035] As shown in FIG. 4, programmable current mirror 320 includes fourselectable current source circuits. The four selectable current sourcecircuits are each controlled by one bit of the digital control word. Forexample, current source transistor 424 is controlled by signal B1 onnode 428, current source transistor 434 is controlled by signal B2 onnode 438, and current source transistor 444 is controlled by signal B3on node 448. Nodes 412, 428,438, and 448 correspond to the “n” bits ofnode 224 (FIG. 3). The output current I_(OUT) is equal to the sum of thecurrents provided by each current source transistor. The ratio ofI_(OUT) to I_(IN) is referred to as the “current gain” of theprogrammable current mirror.

[0036] In embodiments represented by FIG. 4, current source transistors408, 424, 434, and 444 are sized in a binary fashion. For example,transistor 408 has a size of “W,” transistor 424 has a size of “2W,”transistor 434 has a size of “4W,” and transistor 444 has a size of“8W.” In these embodiments, the current gain of programmable currentmirror 320 increases linearly as the digital control word B counts up.In other embodiments, the current source transistors are sized in afashion other than binary. For example, in some embodiments, eachcurrent source transistor is the same size. In these embodiments, thecurrent gain increases linearly as the number of asserted bits in thedigital control word increases linearly. Many other programmable currentmirror embodiments exist, and these embodiments are intended to bewithin the scope of the present invention.

[0037] In embodiments represented by FIG. 4, programmable current mirror320 is implemented using n-channel metal oxide semiconductor fieldeffect transistors (NMOSFETs). Many embodiments of programmable currentmirror 320 exist. In some embodiments, programmable current mirror 320is implemented using bipolar transistors. In other embodiments,programmable current mirror 320 is implemented using junction fieldeffect transistors (JFETs). Programmable current mirror 320 can beimplemented in many other ways without departing from the scope of thepresent invention.

[0038]FIG. 5,shows an integrated circuit having a voltage multiplierwith multiple inputs. Integrated circuit 500 includes V-I converters 502and 506, current multipliers 504 and 508, load devices 510 and 512, andprocessor 520.

[0039] V-I converter 502 receives a differential input voltage (V_(IN1))and outputs a differential current (I₁) that satisfies the followingequation:

I₁=α₁V_(IN1)  (5)

[0040] Current multiplier 504 receives the differential current I₁, andproduces an output current (I_(B)) that satisfies the followingequation:

I_(B)=K_(B)α₁V_(IN1)  (6)

[0041] V-I converter 506 receives a differential input voltage (V_(IN2))and outputs a differential current (I₂) that satisfies the followingequation:

I₂=α₂V_(IN2)  (7)

[0042] Current multiplier 508 receives the differential current 12, andproduces an output current (I_(D)) that satisfies the followingequation:

I_(D)=K_(D)α₂V_(IN2)  (8)

[0043] Current multipliers 504 and 508 each have differential outputnodes that are coupled in common to output nodes 530 and 532. As aresult, the output currents of current multipliers 504 and 508 sum atoutput nodes 530 and 532. Load devices 510 and 512 produce adifferential voltage as a result of the differential output current.Assuming that the load devices have an impedance equal to R_(LOAD), thedifferential output voltage equals:

V_(OUT)=R_(LOAD)(K_(B)α₁V_(IN1)+K_(D)α₂V_(IN2))  (9)

[0044] As shown in equation (9) above, the voltage multiplier of FIG. 5multiplies each input voltage by a constant value and sums the resultingvoltage values. The constant values used to scale the input voltages areequal to a product of the gain of the corresponding V-I converter andcurrent multiplier. By varying the gain of the V-I converters and thegain of the current multipliers, the input voltage scaling can bechanged.

[0045] The current gain of current multiplier 504 is controlled by thedigital word shown as “B,” and the current gain of current multiplier508 is controlled by the digital word shown as “D.” Each of currentmultipliers 504 and 508 can be implemented using current multiplierembodiments described above, and can also be implemented using alternatecurrent multiplier embodiments.

[0046] Integrated circuit 500 includes processor 520 to provide thedigital control words to the current multipliers. Processor 520 can beany type of suitable processor capable of providing digital controlwords. Examples include, but are not limited to, microcontrollers,digital signal processors, and microprocessors. In some embodiments,processor 520 is omitted. In some of these embodiments, registers areused to hold the digital control words. The registers can be loadedusing any known mechanism, including as memory-mapped peripherals, scanchains, or the like.

[0047] Each V-I converter in integrated circuit 500 is coupled to acorresponding current multiplier. For example, V-I converter 502 iscoupled to current multiplier 504 and V-I converter 506 is coupled tocurrent multiplier 508. Two V-I converters and current multipliers areshown in FIG. 5. In some embodiments, more than two V-I converters andcurrent multipliers exist. In these embodiments, more than two inputvoltages are received, and more than two differential currents aresummed at the load devices. Any number of V-I converters and currentmultipliers can exist in parallel without departing from the scope ofthe present invention.

[0048] The various voltage multiplier embodiments described hereinoperate with good linearity and at high frequencies. In some embodimentswith power supply values of 1.6 volts, good linearity is achieved over adifferential input voltage swing of 0.8 volts. Also in some embodiments,settling times are on the order of a few hundred picoseconds.

[0049] Integrated circuits 200 (FIG. 2) and 500 (FIG. 5) can be anyintegrated circuit capable of including any of the voltage multipliercircuit embodiments described herein. Integrated circuits 200 and 500can be a processor such as a microprocessor, a digital signal processor,a microcontroller, or the like. Integrated circuits 200 and 500 can alsobe an integrated circuit other than a processor such as anapplication-specific integrated circuit (ASIC), a processor peripheral,a communications device, a memory controller, or a memory such as adynamic random access memory (DRAM).

[0050] It is to be understood that the above description is intended tobe illustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reading and understanding theabove description. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. A circuit comprising: a voltage-to-currentconverter having a differential input node and a differential outputnode; and a current multiplier coupled to the differential output nodeof the voltage-to-current converter circuit.
 2. The circuit of claim 1wherein the current multiplier includes an output node, the circuitfurther comprising a load device coupled to the output node of thecurrent multiplier.
 3. The circuit of claim 1 further comprising: asecond voltage-to-current converter having a differential input node anda differential output node; and a second current multiplier coupled tothe differential output node of the second voltage-to-current converter;wherein the current multiplier and the second current multiplier eachhave differential output nodes coupled in common.
 4. The circuit ofclaim 3 further comprising a pair of loads coupled to the differentialoutput nodes of the current multiplier and the second current multiplierto develop a differential output voltage.
 5. The circuit of claim 3wherein the current multiplier comprises: a diode-connected controltransistor; and a plurality of selectable current source circuitscoupled to the diode-connected control transistor.
 6. The circuit ofclaim 5 wherein each of the plurality of selectable current sourcecircuits includes: a current source transistor having a gate; and aselect transistor coupled source-to-drain between a gate of thediode-connected control transistor and the gate of the current sourcetransistor.
 7. The circuit of claim 1 wherein the current multiplierincludes a plurality of selectable current source circuits to provide adigitally controlled programmable gain.
 8. The circuit of claim 7further comprising: a second voltage-to-current converter; and a secondcurrent multiplier having a digitally programmable current gain, thesecond current multiplier coupled to be responsive to the secondvoltage-to-current converter circuit and having an output node coupledin common with an output node of the current multiplier.
 9. The circuitof claim 7 wherein the circuit comprises a plurality ofvoltage-to-current converters and a plurality of current multipliers,each of the plurality of voltage-to-current converters being coupled toa corresponding one of the plurality of current multipliers, and whereinthe plurality of current multipliers have output nodes coupled incommon.
 10. The circuit of claim 9 further comprising a load devicecoupled to the output nodes coupled in common.
 11. A circuit comprising:a differential pair of input transistors to convert a differential inputvoltage into a first differential current; a current multiplier coupledto the differential pair of transistors to produce a second differentialcurrent in response to the first differential current; and a pair ofload devices to produce a differential output voltage in response to thesecond differential current.
 12. The circuit of claim 11 wherein thecurrent multiplier includes a plurality of selectable current sourcecircuits.
 13. The circuit of claim 12 wherein each of the plurality ofselectable current source circuits is configured to be responsive to adigital control signal.
 14. The circuit of claim 11 further comprising:a second differential pair of transistors to receive a seconddifferential input voltage; and a second current multiplier coupledbetween the second differential pair of transistors and the pair of loaddevices.
 15. The circuit of claim 14 wherein the second currentmultiplier is configured to vary a differential output current inresponse to a second set of digital control signals.
 16. An integratedcircuit comprising a voltage multiplier circuit that includes a currentmultiplier with a digitally programmable current gain.
 17. Theintegrated circuit of claim 16 further comprising a voltage-to-currentconverter circuit coupled to an input side of the current multiplier.18. The integrated circuit of claim 17 further including a processorcoupled to the current multiplier to provide a digital value such thatan output current of the current multiplier is responsive to the digitalvalue and a voltage input to the voltage-to-current converter circuit.19. The integrated circuit of claim 16 wherein the current multipliercomprises a plurality of current mirrors with digitally programmablegain, each of the plurality of current mirrors having a common outputnode.
 20. The integrated circuit of claim 19 further comprising aplurality of voltage-to-current converter circuits, wherein each of theplurality of voltage-to-current converter circuits is coupled to acorresponding one of the plurality of current mirrors.
 21. Theintegrated circuit of claim 20 further comprising a load device coupledto the common output node to produce an output voltage from a sum ofcurrent mirror output currents.
 22. The integrated circuit of claim 16wherein the integrated circuit is a circuit type from the groupcomprising: a processor, a processor peripheral, a memory, and a memorycontroller.
 23. An integrated circuit comprising: a plurality ofvoltage-to-current converters to receive a plurality of differentialinput voltages and produce a plurality of differential currents; and aplurality of current multipliers coupled to a common output node, eachof the plurality of current multipliers coupled to a corresponding oneof the plurality of voltage-to-current converters to receive acorresponding one of the plurality of differential currents.
 24. Theintegrated circuit of claim 23 further comprising a load device coupledto the common output node to produce an output voltage.
 25. Theintegrated circuit of claim 23 wherein each of the plurality of currentmultipliers has a programmable current gain.
 26. The integrated circuitof claim 25 wherein each of the plurality of current multipliersincludes a digital input port to influence the programmable currentgain.
 27. The integrated circuit of claim 25 further comprising aprocessor coupled to the plurality of current multipliers to set theprogrammable current gain.
 28. The integrated circuit of claim 23wherein the integrated circuit is a circuit type from the groupcomprising: a processor, a processor peripheral, a memory, and a memorycontroller.